delay lock loop中文是什么意思

• 延迟锁定环

• "delay"中文翻译    vt. 延迟，拖延，耽搁。 We'll delay th ...
• "lock"中文翻译     lock2 n. 1.一绺卷发。 〔pl.〕 ...
• "loop"中文翻译    n. 1.(用线、带等打成的)圈，环，匝，框，环孔，线圈 ...
• "delay lock loop，dll" 中文翻译 :    延迟锁定回路
• "delay-lock loop" 中文翻译 :    迟延锁定环
• "dll delay lock loop" 中文翻译 :    延迟锁定环路
• "delay lock" 中文翻译 :    延迟锁定
• "lock loop" 中文翻译 :    锁定环; 锁环
• "lock-loop" 中文翻译 :    绞绕线圈(针织); 锁定环
• "loop lock" 中文翻译 :    环阻
• "phase lock loop lock on time" 中文翻译 :    锁相环锁定时间
• "delay loop spore" 中文翻译 :    延迟循环存储
• "delay loop store" 中文翻译 :    延迟循环存储
• "delay-free controller loop" 中文翻译 :    无延迟控制器回路
• "loop delay time" 中文翻译 :    回路延迟时间
• "long wire-lock loop" 中文翻译 :    长线锁环路
• "loose phase-lock loop" 中文翻译 :    弱锁相回路
• "phase lock loop" 中文翻译 :    锁相环路; 锁相回路
• "phase lock loop pull in" 中文翻译 :    锁相环牵引
• "phase-lock loop" 中文翻译 :    锁相环路; 相位同步回路
• "rf phase-lock loop" 中文翻译 :    射频锁相环
• "closed loop phase lock system" 中文翻译 :    闭环锁相系统
• "opll optical phase lock-loop" 中文翻译 :    光锁相环路
• "phase lock loop cycle slipping" 中文翻译 :    锁相环周期滑动
• "phase lock loop hold in range" 中文翻译 :    锁相环跟踪范围

• Firstly , the principle and realization of the step acquisition and delay locked loop are discussed
  首先，论文讨论了步进捕获延迟锁定环的原理及实现机理。
• The principle of large step fast acquisition and the circuit design of large step fast acquisition delay lock loop ( lsdll ) are disgussed as the emphasis
  本文着重从理论和电路设计两方面对大步进快速捕获方法和大步进快速捕获延迟锁定环进行讨论。
• In the second part , some of the multipath mitigation techniques widely used presently are analysed and compared with each other , from which we select the medll ( multipath estimating delay lock loop ) technique as the multipath mitigation algorithm in scope of signal processing in the receivers
  第二部分通过对目前常用的多径消除技术进行分析与比较,选择了medll技术作为接收机信号处理阶段的多径消除算法。
• There are two uncertain factor about it : the phase of the pn code and the doppler - shift . after capturing the received signal successfully , the traditional ds receiver always uses a delay locked loop ( dll ) to synchronize the pn code and then uses a costas loop to realize the carrier synchronization . this complex closed - loop structure not only take long time to realize the synchronization , but also has the defect of “ hang up ”
  传统的扩频接收机通常在捕获伪码信号后利用迟早门鉴相的延时锁定环来实现伪码的精同步,解扩后利用科斯塔斯环实现载波同步,这种闭环结构不仅同步时间长、结构复杂,而且锁相环还存在所谓的“ hang - up ”现象。
• Chapter one introduces the recent development of usb2 . 0 and the overall architecture of transceiver interface ; chapter two proposes the design flow and design style ; chapter three presents the whole system and module partition ; chapter four emphasizes on the dual - mode transmitter circuit , and gives out the simulation waveforms ; chapter five focuses on the design of over - sampling receiver and dll ( delay locked loop ) module ; chapter six designs the band - gap reference circuit . in the end , it concludes the design , and estimates the trend of usb . the dissertation is emphasized on dual - mode transmitter architecture , implementation of high speed dll using dba ( digital - based analog ) technology and a new design methodology for complex digital modules in mixed - signal circuit
  本文第一章介绍了usb2 . 0的发展现状和收发器接口芯片系统；第二章介绍了该芯片的设计流程和风格；第三章介绍了该接口芯片的总体构架以及模块划分；第四章着重介绍双模发送器电路设计并给出了仿真验证波形；接下来第五章分析了过采样接收器的设计并对其中的dll ( delaylockedloop )模块设计进行了详细的分析；第六章介绍了本芯片内置的基准电压源的设计；最后对本文的设计一个总的回顾和总结，并展望下一代usb的发展方向。
• By complementing the proposed scheme with methods to estimate the fractional code delay , the acquisition unit an provide high quality delay estimates such that it can instead of the delay locked loop in the traditional ds receiver . after dispreading successfully , this dissertation introduces a method to estimate the doppler - shift directly from some samples based maximum likelihood estimation , and then revise it forwardly
  在成功解扩之后,本文利用最大似然估计从l个样点中直接估计出残余多普勒频偏,并进行前向频偏校正,来代替传统扩频接收机中的科斯塔斯环,经仿真证明该方法的估计精度完全满足解调的要求。
• The clock recovery block of usb2 . 0 transceiver macrocell consists of phase locked circuit , such as pll and dll ( delay locked loop ) . this block use external crystal 12mhz sin signal to produce 60mhz , 120mhz , 480mhz clock signal , and can recover colock signal form date wave . it can support 480mbps ( hs ) and 12mbps ( fs ) word speeds as defined in usb2 . 0 specification .
  目的是用锁相环电路? pll和dll (延迟锁相环)实现usb2 . 0收发器宏单元utm的时钟恢复模块。其中pll环路构成的时钟发生器将外部晶振的12mhz正弦信号生成60mhz 、 120mhz 、 480mhz等本地时钟信号。 dll环路依据本地时钟信号对外部数据信号进行时钟恢复。
• It consists of three main parts : in the first part , we analyse the effect of multipath on code - tracking loops of receivers in spread - spectrum ranging systems . first , we establish the model of received signals with the present of multipath through the presentation of multipath ’ s characters . then , we analyse the theory of delay lock loop ( dll ) , based on which we derive the tracking error of dll caused by multipath
  首先通过对多径信号特性的分析得到存在多径时的接收信号模型,然后在对扩频测距系统的延迟锁定环路( delaylockloop )工作原理的分析的基础上,阐明了多径存在时码跟踪环路产生误差的机理。